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commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 1 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved note 1 the timing specification of high speed bin is backward compat ible with low speed bin . note 2 violating trfc specification will induce malfunction. note 3 trefi values for all bank refresh is within temperature specification (<= 85 ). commercial mobile ddr 1g b sdram ? jedec lp ddr compliant - low power consumption - 2 n prefetch architecture - differential clock inputs (ck and ?? ) - double - data rate on dqs, dqs and dm - commands entered on each positive ck edge - dqs edge - aligned with data for reads; center - aligned with data for writes - status register read (srr) ? signal integrity - configurable ds for system compatibility ? cas latency ( 2, 3 ) ? burst length ( 2, 4, 8, 16 ) programmable f unctions features density and addressing item 1gb addressing standard reduced page s ize organization 64m x 16 32m x 32 32m x 32 number of banks 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a10/ap a10/ap a10/ap row address a0 - a13 a0 - a12 a0 - a13 column address a0 - a9 a0 - a 9 a0 - a 8 trfc(ns) 2 72 72 72 trefi (s) 3 7.8 7.8 7. 8 packages / density i nformation lead - free rohs compliance and halogen - fre e 1gb ( org. / package) length x width (mm) ball pitch (mm) 64 mx16 60 - ball v fbga 8 .00 x 9 .00 0.8 0 32 mx 32 9 0 - ball v fbga 8 .00 x 13 .00 0.8 0 ? speed grade ( cl - trcd - trp ) 1 - 333 mbps / 3 - 3 - 3 - 400 mbps / 3 - 3 - 3 options nanya technology corp. nt6d m 64 m 16 bd / nt6d m 32 m 32 bc ? burst t ype (sequential , interleave d ) ? driver strength (full, 1/2, 3/4, 1/4) ? dat a integrity - dram built - in temperature sensor for temperature compensated self refresh (tcsr) - auto refresh and self refresh mode s ? power saving mode - deep power down mode (dpd) - partial array self refresh (pasr) - clock stop capability during idle pe riod ? lvcmos interface and power supply - vd d/vddq= 1.70 to 1.95v ? temperature range ( t c ) - commercial grade = - 25 ~ 85 ntc has the rights to change any sp ecifications or product without notification.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 2 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved description s the 1 gb mobile lpddr sdram is a high - speed cmos, dynamic random - access memory containing 1 , 073 , 741 , 824 bits. it is internally configured as a qua d - bank dram. the 1 gb chip is organized as 16 mbit x 4 banks x 16 i/o or 8 mbit x 4 banks x 32 i/o device. each of the x16s 268 , 435 , 456 - bit banks is organized as 16 , 384 rows by 1 ,0 24 columns by 16 bits. each of the x32s 268 , 435 , 456 - bit banks is organized as 8 , 192 rows by 1,024 columns by 32 bits . in the reduced page - size option, each of the x32 s 268,435,456 - bit banks are organized as 16,384 rows by 512 columns by 32 bits. to achieve high - speed operation, our lpddr sdram uses the double data rate architecture and adopt 2n - prefetch interface desig ned to transfer two data per clock cycle at the i/o pins. the chip is designed to comply with all key mobile double - data - rate sdram key features. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks, and latched at the cross point of dif ferential clocks (ck risi ng and ?? e input data is registered at both edges of dqs, and the output data is referenced to both edges of dqs, as well as to both edges of ck. dqs is a bidirectional data strob e signal, transmitted by the lpddr sdram during reads (edge - aligned with data), and by the memory controller during writes (center - aligned with data). lpddr sdram, read and write access are burst oriented. the address bits registered coincident with the a ctive command to select the row in the specific bank. and then the address bits registered with the read or write command to select the starting column location in the bank for the burst access. the burst length can be programmed as 2, 4 , 8 or 16 . an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of burst access. lpddr sdram with auto refresh mode, and the power - down mode for power saving. and the deep power down mode can achieve the maximum power r eduction by removing the memory array power within low power ddr sdram. with this feature, the system can cut off almost all dram power without adding the cost of a power switch and giving up month - board power - line layout flexibility. self refresh mode wit h temperature compensated self refresh (tcsr) and partial array self refresh (pasr) options, which allow users to achieve additional power saving. the tcsr and pasr options can be programmed via the extended mode register. the two features may be combined to achieve even greater power saving. the dll that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. all inputs are lvcmos compatible. devices will have a v dd and v ddq supply of 1.8v (nom inal).
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 3 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved ordering information lead - free rohs compliance and halogen - fre e organization part number package speed tc k (ns) clock (mhz) data rate (mb/s/pin) cl commercial grade 64 mx16 nt6dm64m16bd - t 1 60 ball 5.0 200 400 3 nt6dm64m16bd - t 3 6.0 166 333 3 32 mx32 nt6dm32m32bc - t 1 90 ball 5.0 200 400 3 nt6dm32m32bc - t 3 6.0 166 333 3
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 4 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved n anya t echnology product family 6s = lp sdr sdr am 6d =lp ddr sdram 6v = lp ddr2 - s2 sdram 6t = lp ddr2 - s4 sdram 6x = lpsdr/ddr comb 6y = lp ddr2 - s2/s4 comb nanya mobile component /wafer part numbering guide nt 6d m 64 m16 b d t1 package code g = 54 - ball bga (lpsdr, x16) d = 60 - ball bga (lpddr , x16 ) k = 90 - ball bga (lpsdr , x32 ) c = 9 0 - ball bga (lpddr , x32 ) a = 7 9 - ball bga (lpddr2 , x16 ) i = 134 - ball bga (lpddr2, x32) q = 168 - ball pop - fbga (lpddr2) r = 216 - ball pop - fbga (lpddr2) 3 = 240 - ball pop - fbga (lpddr2) 5 = 220 - ball pop - fbga (lpddr2) 0 = wafer (kgd) speed lpsdr s1 = 166mhz @ cl=3 s2 = 133mhz @ cl=3 lpddr t1 = 5.0ns @ cl=3 t2 = 5.4ns @ cl=3 t3 = 6.0ns @ cl=3 t4 = 7.5ns @ cl=3 t 5 = t3 & s2 t 6 = t1 & s1 lpddr2 - s2 t1 = 5.0ns @ rl=3 t 3 = 6.0 ns @ rl=3 lpddr2 - s4 g 0 = 1.8 ns @ rl= 8 g1 = 2.5ns @ rl=6 g2 = 3.0ns @ rl=5 g3 = 3.7ns @ rl= 4 g4 = 5.0ns @ rl=3 device version a = 1 st version b = 2 nd version c = 3 rd version organization (depth, width): m=mono; t=ddp 1 ; f= qdp 2 256mb = 16m16 = 8m32 = 8m32r 3 512mb = 32m16 = 16m32 = 16m32r 1gb = 64m16 = 32m32 = 32m32r 2gb = 256m8 = 128m16 = 64m32 = 64m32r 4gb = 256m16 = 128m32 = 64t64 8gb = 128f64 = 256f32 = 128t64 = 256t32 grade n/a =commercial grade interface & power (v dd & v ddq ) m = lvcmos (1.8v, 1.8v) n = lvcmos (1.8v, 1.2v) interface & power (v dd1 , v dd2 , v ddq , v ddca ) l = hsul_12 (1.8v, 1.2v, 1.2v, 1.2v) h = hsul_12 (1.8v, 1.35v, 1.2v, 1.2v)
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 5 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved ball assignments and package outline drawing lpddr sdram x16 in vfbga - 60 (8mm x 9mm) note 1: test must be tied to vss or vssq in normal operations. unit: mm * bsc ( b asic s pacing between c enter ) 1 2 3 7 8 9 a vss dq15 vssq vddq dq0 vdd b vddq dq13 dq14 dq1 dq2 vssq c vssq dq11 dq12 dq3 dq4 vddq d vddq dq9 dq10 dq5 dq6 test 1 e vssq udqs dq8 dq7 ldqs vddq f vss udm nc a13 ldm vdd g cke ck ?? we ?as ras h a9 a11 a12 ?s ba0 ba1 j a6 a7 a8 a10/ap a0 a1 k vss a4 a5 a2 a3 vdd
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 6 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved ball assignments and package outline drawing lpddr sdram x32 in vfbga - 90 (8mm x 13mm) note 1 : a13 is only available for reduced page - size configuration. note 2 : test mu st be tied to vss or vssq in normal operations. unit: mm * bsc ( b asic s pacing between c enter )
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 7 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved ball description s symbol 1 type function ck, ?? input clock: ck and ?? are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ?? . input and output data is referenced to the crossing of ck and ?? (both directions of crossing). internal clock signals are derived from ck, ?? . cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power - down and self r efresh operation (all banks idle), or active powerdown (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. input buffers, excluding ck, ?? and cke, are disabled during power - down an d self refresh mode which are contrived for low standby power consumption. ?s ? input chip select: ?s enables (registered low) and disables (registered high) the command decoder. all commands are masked when ?s is registered high. ?s provides for external b ank selection on systems with multiple banks. ?s is considered part of the command code. ras , ?as , we ? input command inputs: ras , ?as and we (along with ?s ) define the command being entered. dm for x16 , ldm, udm for x32 , dm0 - dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input - only, the dm loading matches the dq and dqs loading. for x 16 devices, ldm corresponds to the data on dq0 - dq7, udm corresponds to the data on dq8 - dq15. for x32 devices, dm0 corresponds to the data on dq0 - dq7, dm1 corresponds to the data on dq8 - dq15, dm2 corresponds to the data on dq16 - dq23, and dm3 corresponds to the data on dq24 - dq31. dq for x16: dq0 - dq15 for x32: dq0 - dq31 input/output data bus: bi - directional input / output data bus. dqs for x16: ldqs, udqs for x32: dqs0 - dqs3 input/output data strobe: output with read data, input with write data. edge - aligned with read data . c entered with write data to capture write data. for x16 device, ldqs corresponds to the data on dq0 - dq7, udqs corresponds to the data on dq8 - dq15. for x32 device, dqs0 corresponds to the data on dq0 - dq7, dqs1 corresponds to the data on dq8 - dq15, dqs2 corresponds to the data on dq16 - dq23, and dqs3 corresponds to the data on dq24 - dq31. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register is loaded during a load mode register command.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 8 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved symbol 1 type function a1 3 - a0 input address inputs: provide the row address for active commands, and the column address and auto precharge bit(a10) for read or write commands, to selec t one location out of the memory array in the respective bank. during a precharge command, a10 determines whether the precharge applies to one bank (a10 low, bank selected by bank address inputs ) or all banks (a10 high). the address inputs also provide the opcode during a mode register set command. nc - no connect: these pins should be left unconnected. vddq supply dq power supply : isolated on the die for improved noise immunity. vssq supply dq ground: provide isolated ground to dqs for improved noise im munity. vdd supply power supply vss supply ground notes : 1. the differential signal may show up in a different symbol but it indicate s to the same thing . e.g., /ck = ck# = ?? = ckb , /dqs = dqs# = ??s = dqsb
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 9 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved functional block diagram C lp d dr 64m x 16
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 10 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved functional block diagram C lp d dr 32m x 32
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 11 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved simplified state diagram abbrev . function abbrev . function abbrev . function act active lmr load mode register pre precharge read read (w/o autoprecharge) ckeh exit power - down preall precharge all b anks read a read (w/ autoprecharge) ckel enter power - down aref auto refresh write write (w/o autoprecharge) dpd enter deep power down sref enter self refresh write a write (w/ autoprecharge) dpdx exit deep power down srefx exit self refresh emr load ex tended mode register bst burst terminate srr status register read
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 12 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved electrical specifications absolute maximum dc ratings symbol parameter min max units v dd / v ddq v dd / v ddq supply voltage relative to vss - 1.0 2.4 v vin voltage on any pin relative to v ss - 0.5 2.4 or (v ddq + 0.3v), whichever is less v tstg storage temperature (plastic) - 55 +150 ? notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temper ature is the case surface temperature on the center/top side of the dram. 3. v dd and v ddq must be within 300mv of each other at all times. v ddq must not exceed v dd . input / output capacitance symbol parameter min max unit notes cck input capacitance: ck , ?? ?? notes: 1. these values are guaranteed by design and are tested on a sample base only. 2. these capacitance values are for single monolithic devices only. multiple die packages will have parallel capacitive loads. 3. input capacitance is measured according to jep147 procedure for measuring capacitance using a vector network analyzer. vdd, vddq are applied and all other pins (except the pin under test) floating. dqs should be in high impedance state. this may be achieved by pulling cke to low level. 4. although dm is an input - only pin, the input capacitance of this pin must model the input capacitance of the dq and dqs pins. this is required to match signal propagation times of dq, dqs and dm in the system.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 13 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved ac/dc electrical characteristics and operating conditions apply note 1 - 3 to whole the table. symbol parameter min max unit notes v dd supply voltage 1.7 0 1.9 5 v - v ddq i/o supply voltage 1.7 0 1.9 5 v - address and command inputs v ih input voltage high 0.8 x v ddq v ddq + 0.3 v - v il input voltage low - 0.3 0.2 x v ddq v - clock inputs (ck, ?? ) v in dc input voltage - 0.3 v ddq + 0.3 v - v id(dc) dc input differential voltage 0.4 x v ddq v ddq + 0.6 v 2 v id(ac) ac input differential voltage 0.6 x v ddq v ddq + 0.6 v 2 v ix ac differential crosspoint voltage 0.4 x v ddq 0.6 x v ddq v 3 data inputs v ih(dc) dc input high voltage 0. 7 x v ddq v ddq + 0.3 v - v il(dc) dc input low voltage - 0.3 0.3 x v ddq v - v ih(ac) ac input high voltage 0.8 x v ddq v ddq + 0.3 v - v il(ac) ac input low voltage - 0.3 0.2 x v ddq v - data outputs v oh dc output high voltage: logic 1 (i oh = - 0.1ma) 0. 9 x v ddq - v - v ol dc output low voltage: logic 0 (i ol = - 0.1ma) - 0.1 x v ddq v - leakage current i i input leakage current any input 0 Q in Q dd , all other pins not under test = 0v - 1 1 ua i oz output leakage current dqs are disabled; 0 Q out Q ddq - 5 5 ua notes: 1. all voltages referenced to vss and vssq must be same potential. 2. vid(dc) and vid(ac) are the magnitude of the differen ce between the input level on ck and the input level on ?? . 3. the value of vix is expected to be 0.5 * vddq and must track variations in the dc level of the same.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 14 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved idd specifications and measurement conditions (64mx16) notes 1 C 5 apply to all the parameter s/conditions in this table symbol parameter/condition t1( - 5) lpddr400 t3( - 6) lpddr333 unit notes idd0 operating one bank active - precharge current: trc = trcmin; tck = tckmin; cke is high; ?s is high between valid commands; address inputs are switching; da ta bus inputs are stable 100 90 ma 6 idd2p precharge power - down standby current: all banks idle, cke is low; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 400/600 (typ./max.) ua 7,8 idd2ps precharge power - down standby current with clock stopped: all banks idle, cke is low; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 400/600 (typ./max.) ua 7 idd2n precharge non power - down standby current: all banks i dle, cke is high; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 18 15 ma 9 idd2ns precharge non power - down standby current with clock stopped: all banks idle, cke is high; ?s is high, ck = low, ck = high; a ddress and control inputs are switching; data bus inputs are stable 14 8 ma 9 idd3p active power - down standby current: one bank active, cke is low; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 5 ma 8 idd3 ps active power - down standby current with clock stopped: one bank active, cke is low; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 5 ma idd3n active non power - down standby current: one bank active, cke is high; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 20 18 ma 6 idd3ns active non power - down standby current with clock stopped: one bank active, cke is high; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 16 14 ma 6 idd4r operating burst read current: one bank active; bl=4; cl=3; tck = tckmin; continuous read bursts; i out = 0 ma address inputs are switching; 50% data change each burst transfer 1 35 120 ma 6 idd4w operating burst write current: one bank active; bl=4; tck = tckmin; continuous write bursts; address inputs are switching; 50% data change each burst transfer 135 120 ma 6 idd5 auto refresh current: tck = tckmin; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable trc = 1 4 0ns 100 100 ma 10 idd5a trc = trefi 15 15 ma 10,11 idd8 deep power - down current: address and control inputs are stable; data bus inputs are stable 25 o c 10 ua 7 ,13 85 o c 25 ua 7
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 15 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved idd specifications and measurement conditions (32mx32) notes 1 C 5 apply to all the parameters/conditions in this table symbol parameter/condition t1( - 5) lpddr400 t3( - 6) lpddr333 unit notes idd0 operating one bank active - precharge current: trc = trcmin; tck = tckmin; cke is high; ?s is high between valid commands; address inputs are switching; data bus inputs are stable 100 90 ma 6 idd2p precharge power - down standby current: all banks idle, cke is low; ?s is high, tck = tckmin; address and cont rol inputs are switching; data bus inputs are stable 400/600 (typ./max.) ua 7,8 idd2ps precharge power - down standby current with clock stopped: all banks idle, cke is low; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 400/600 (typ./max.) ua 7 idd2n precharge non power - down standby current: all banks idle, cke is high; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 18 15 ma 9 idd2ns precharge non power - down standby current with clock stopped: all banks idle, cke is high; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 14 8 ma 9 idd3p active power - down standby current: one bank active, cke is low; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 5 ma 8 idd3ps active power - down standby current with clock stopped: one bank active, cke is low; ?s is high, ck = low, ck = high; address and control inputs are sw itching; data bus inputs are stable 5 ma idd3n active non power - down standby current: one bank active, cke is high; ?s is high, tck = tckmin; address and control inputs are switching; data bus inputs are stable 20 18 ma 6 idd3ns active non power - down st andby current with clock stopped: one bank active, cke is high; ?s is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 16 14 ma 6 idd4r operating burst read current: one bank active; bl=4; cl=3; tck = tckmin; continuous read bursts; i out = 0 ma address inputs are switching; 50% data change each burst transfer 150 135 ma 6 idd4w operating burst write current: one bank active; bl=4; tck = tckmin; continuous write bursts; address inputs are switching; 50% data c hange each burst transfer 150 135 ma 6 idd5 auto refresh current: tck = tckmin; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable trc = 1 4 0ns 100 100 ma 10 idd5a trc = trefi 15 15 ma 10,11 idd8 deep power - down current: address and control inputs are stable; data bus inputs are stable 25 o c 10 ua 7 ,13 85 o c 2 5 ua 7
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 16 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved idd6 self - refresh and partial array refresh) current notes 1 C 5, 7, and 12 apply to all the parameters/conditions in this table symbol parame ter/condition temperature pasr typical max unit idd6 self refresh current: cke=low; t ck= t ck(min); address and control inputs are stable; data bus inputs are stable. 85 full array 1000 1200 ua 1/2 array 700 ua 1/4 array 560 ua 45 full array 500 ua 1/2 array 400 ua 1/4 array 350 ua idd notes: 1. all voltages referenced to v ss . 2. tests for i dd may be conducted at nominal supply voltage levels , but the related specifications and device operation are guaranteed for the full voltage and temperature range specified. 3. timing and i dd tests may use a v il - to - v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ddq /2 (or, to the crossing point for ck and ?? ). the output timing reference voltage level is v ddq /2. 4. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time with the outputs open. 5. i dd specifications are tested after the device is properly initializ ed, and are averaged at the defined cycle rate. 6. min ( t rc or t rfc) for idd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for idd measurements is the largest multiple of t ck that m eets the maximum absolute value for t ras. 7. measurement is taken 500ms after entering into this operating mode to provide settling time for the tester. 8. v dd must not vary more than 4 % if cke is not active while any bank is active. 9. idd2n specifies dq, dqs, an d dm to be driven to a valid high or low logic level. 10. cke must be active (high) during the entire time a refresh command is executed. from the time the auto refresh command is registered, cke must be active at each rising clock edge until t rfc later. 11. this limit is a nominal value and does not result in a fail. cke is high during refresh command period ( t rfc [min]) else cke is low (for example, during standby). 12. values for idd6 85c are guaranteed for the entire temperature range. 13. idd8 are typical values. i dd8 is measured at 25 .
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 17 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved electrical characteristics and recommended ac operating conditions n ote 1 - 9 apply to all of the parameters symbol parameter t1 ( - 5 ) lpddr400 t3 ( - 6 ) lpddr333 unit notes min max min max tac access window of dqs from c k , ? ? cl=3 2.0 5.0 2.0 5.5 ns cl=2 2.0 6.5 2.0 6.5 tck clock cycle time cl=3 5.0 - 6 - ns 12 cl=2 12 - 12 - tch ck high - level width 0.45 0.55 0.45 0.55 tck tcl ck low - level width 0.45 0.55 0.45 0.55 tck thp half - clock period tch , tcl - tch , tc l - ns 10,11 tcke cke min. pulse width (high and low) 1*tck - 1*tck - ns tdqsck access window of dqs from ck, ?? cl=3 2.0 5.0 2.0 5.5 ns cl=2 2.0 6.5 2.0 6.5 ns tdqsq dqs - dq skew, dqs to last dq valid, per group, per access - 0.4 - 0.45 ns 20 tqh s data hold skew factor - 0.5 - 0.65 ns 11 tqh dq - dqs hold, dqs to first dq to go non - valid, per access thp - tqhs - thp - tqhs - ns 11 n/a data valid output window (dvw) t qh C t dqsq t qh C t dqsq ns th z data - out high - z window from ck, ?? cl=3 - 5.0 - 5. 5 ns 19 cl=2 - 6.5 - 6.5 ns t lz data - out low - z window from ck, ?? 1.0 - 1.0 - ns 19 trpre dqs read preamble cl=3 0.9 1.1 0.9 1.1 tck 23 cl=2 0.5 1.1 0.5 1.1 tck 23 trpst dqs read postamble 0.4 0.6 0.4 0.6 tck t src read of srr to next valid comm and cl+1 - cl+1 - tck t srr srr - to - read 2 - 2 - tck t tq internal temperature sensor valid temperature output enable 2 - 2 - ms 31 tdh f dq and dm input hold time relative to dqs (fast slew rate) 0. 48 - 0.6 - ns 13,14,15 tdh s dq and dm input hold time r elative to dqs (slow slew rate) 0. 58 - 0.7 - ns 13,14,16 tds f dq and dm input setup time relative to dqs (fast slew rate) 0. 48 - 0.6 - ns 13,14,15 tds s dq and dm input setup time relative to dqs (slow slew rate) 0. 58 - 0.7 - ns 13,14,16 tdipw dq and dm input pulse width (for each input) 1.8 - 2.1 - ns 17
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 18 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved symbol parameter t1 ( - 5 ) lpddr400 t3 ( - 6 ) lpddr333 unit notes min max min max tdqs s write command to first dqs latching transition 0.75 1.25 0.75 1.25 tck td q sh dqs input high pulse width 0.4 0.6 0.4 0.6 tck tdqsl dqs input low pulse width 0.4 0.6 0.4 0.6 tck tdsh dqs falling edge from ck rising C hold time 0.2 - 0.2 - tck tdss dqs falling edge from ck rising C setup time 0.2 - 0.2 - tck twpre dqs write preamble 0.25 - 0.25 - tck twpr e s dqs write preamble setup time 0 - 0 - ns 21 twpst dqs write postamble 0.4 0.6 0.4 0.6 tck 22 t i h f address and control input hold time ( fast slew rate ) 0.9 - 1.1 - ns 15,18 t i h s address and control input hold time ( slow slew rate ) 1.1 - 1.2 - ns 16,18 t i s f address and control input setup time ( fast slew rate ) 0.9 - 1.1 - ns 15,18 t i s s address and control input setup time ( slow slew rate ) 1.1 - 1.2 - ns 16,18 tipw address and control input pulse width 2.3 - 2.6 - ns 17 tmr d load mode register comman d cycle time 2 - 2 - tck tras active to precharge command 40 70,000 41.8 70,000 ns trc active to active / active to auto refresh command period 55 - 60 - ns trcd active to read or write delay 15 - 18 - ns 24 trp precharge command period 15 - 18 - ns 24 trrd active bank - a to active bank - b command 10 - 12 - ns t dal auto precharge write recovery + precharge time - - - - - 26 twr write recovery time 15 - 15 - ns twtr internal write to read command delay 2 - 1 - tck txp exit power - down mode to f irst valid command 6 - 6 - ns 28 txsr exit self refresh to first valid command 112.5 - 112.5 - ns 27 tref refresh period - 64 - 64 ms tref i average periodic refresh interval - 7.8 - 7.8 us 29,30 t rfc auto refresh command period 72 - 72 - ns notes: 1. all voltages referenced to vss. 2. all parameters assume proper device initialization.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 19 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved 3. tests for ac timing, and electrical ac and dc characteristics may be conducted at nominal supply voltage levels, but the rela ted specifications and device operation are g uaranteed for the full voltage range specified. 4. the circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to be either a precise representation of the typical system envir onment or a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to system environment. specifications are correlated to production test conditions (g enerally a coaxial transmission line terminated at the tester electronics). for the half - strength driver with a nominal 10pf load, parameters t ac and t qh are expected to be in the same range. however, these parameters are not subject to production test but are estimated by design/characterization. use of ibis or other simulation tools for system design validation is suggested. 5. the ck , ?? input reference voltage level (for timing referenced to ck , ?? ) is the point at which ck and ?? cross; the input reference voltage level for signals other than ck , ?? is v ddq /2. 6. the timing reference voltage level is vddq/2. 7. ac and dc input and output vo ltage levels are defined in the section for electrical characteristics and ac/dc operating conditions. 8. a ck / ?? differential slew rate of 2.0 v/ns is assumed for all parameters . 9. cas latency definition: with cl = 3 the first data element is valid at (2 * tck + tac) after the clock at which the read command was registered (see figure); with cl = 2 the first data element is valid at (tck + tac) after the clock at which the read com mand was registered; with cl = 4 the first data element is valid at (3 * tck + ta c) after the clock at which the read command was registered.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 20 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch) 11. t qh = thp - tqhs, where thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tcl, tch). tqhs accounts for 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers. 12. the only time that the cl ock frequency is allowed to change is during clock stop, power - down or self - refresh modes. 13. the transition time for dq, dm and dqs inputs is measured between vil(dc) to vih(ac) for rising input signals, and vih(dc) to vil(ac) for falling input signals. 14. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. 15. input slew rate 1.0 v/ns. 16. input slew rate 0.5 v/ns and < 1.0 v/ns. 17. these parameters guarantee device timing but they are not necessarily tested on each device. 18. the transition time for address and command inputs is measured between vih and vil. 19. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 20. tdqsq consists of data pin skew and output patter n effects, and p - channel to n - channel variation of the output drivers for any given cycle. 21. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before the corresponding ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi - z to logic low. if a previous write was in progress, dqs could be high, low, or transitionin g from high to low at this time, depending on tdqss. 22. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 23. a low level on d qs may be maintained during high - z states (dqs drivers disabled) by adding a weak pull - down element in the system. it is recommended to turn off the weak pull - down element during read and write bursts (dqs drivers enabled). 24. speed bin (cl - trcd - trp) = 3 - 3 - 3 25. speed bin (cl - trcd - trp) = 3 - 4 - 4 (all speed bins except lpddr200) 26. tdal = (twr/tck) + (trp/tck): for each of the terms, if not already an integer, round to the next higher integer. 27. there must be at least two clock pulses during the txsr perio d. 28. there must be at least one clock pulse during the txp period. 29. trefi values are depend e nt on density and bus width. 30. a maximum of 8 refresh commands can be posted to any given lpddr, meaning that the maximum absolute interval between any refresh command and the next refresh command is 8*trefi. 31. it s not supported for package level .
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 21 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved output slew rate characteristics parameter min max unit notes pull - up and pull - down slew rate for full strength driver 0.7 2.5 v/ns 1,2 pull - up and pull - down slew rate for t hree - quarters strength driver 0.5 1.75 v/ns 1,2 pull - up and pull - down slew rate for half strength driver 0.3 1.0 v/ns 1,2 output slew rate matching ratio (pull - up to pull - down) 0.7 1.4 - 3 notes: 1. measured with a test load of 20 pf connected to vssq. 2. output slew rate for rising edge is measured between vild(dc) to vihd(ac) and for falling edge between vihd(dc) to vild(ac ). 3. the ratio of pull - up slew rate to pull - down slew rate is specified for the same temperature and voltage, over the entire temp erature and voltage range. for a given output, it represents the maximum difference between pull - up and pull - down drivers due to process variation. ac overshoot/undershoot specification parameter specification maximum peak amplitude allowed for oversho ot 0.5 v maximum peak amplitude allowed for undershoot 0.5 v the area between overshoot signal and vdd must be less than or equal to 3 v - ns the area between undershoot signal and gnd must be less than or equal to 3 v - ns notes: 1. this specification is intended for devices with no clamp protection and is guaranteed by design. ac overshoot and undershoot definition
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 22 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved output drive strength characteristics voltage [v] full drive strength half drive strength three - quarters drive strength pull - down current [ma] pull - up current [ma] pull - down current [ma] pull - up current [ma] pull - down current [ma] pull - up current [ma] min max min max min max min max min max min max 0 .00 0 0 0 0 0 0 0 0 0 0 0 0 0.1 0 2.8 18.53 - 2.8 - 18.53 1.27 8.42 - 1.27 - 8.4 2 1.96 12.97 - 1.96 - 12.97 0.2 0 5.6 26.8 - 5.6 - 26.8 2.55 12.3 - 2.55 - 12.3 3.92 18.76 - 3.92 - 18.76 0.3 0 8.4 32.8 - 8.4 - 32.8 3.82 14.95 - 3.82 - 14.95 5.88 22.96 - 5.88 - 22.96 0.4 0 11.2 37.05 - 11.2 - 37.05 5.09 16.84 - 5.09 - 16.84 7.84 25.94 - 7.84 - 25.94 0.5 0 14 40 - 14 - 40 6.36 18.2 - 6.36 - 18.2 9.8 28 - 9.8 - 28 0.6 0 16.8 42.5 - 16.8 - 42.5 7.64 19.3 - 7.64 - 19.3 11.76 29.75 - 11.76 - 29.75 0.7 0 19.6 44.57 - 19.6 - 44.57 8.91 20.3 - 8.91 - 20.3 13.72 31.2 - 13.72 - 31.2 0.8 0 22.4 46.5 - 22.4 - 46.5 10.16 21.2 - 10.16 - 21.2 15.68 32.55 - 15.68 - 32.55 0.85 23.8 47.48 - 23.8 - 47.48 10.8 21.6 - 10.8 - 21.6 16.66 33.24 - 16.66 - 33.24 0.9 0 23.8 48.5 - 23.8 - 48.5 10.8 22 - 10.8 - 22 16.66 33.95 - 16.66 - 33.95 0.95 23.8 49.4 - 23.8 - 49.4 10.8 22.45 - 10.8 - 22.45 16.66 34.58 - 16.66 - 34.58 1 .00 23.8 50.05 - 23.8 - 50.05 10.8 22.73 - 10.8 - 22.73 16.66 35.04 - 16.66 - 35.04 1.1 0 23.8 51.35 - 23.8 - 51.35 10.8 23.21 - 10.8 - 23.21 16.66 35.95 - 16.66 - 35.95 1.2 0 23.8 52.65 - 23.8 - 52.65 10.8 23.67 - 10.8 - 23.67 16.66 36.86 - 16.66 - 36.86 1.3 0 23.8 53.95 - 23.8 - 53.95 10.8 24.14 - 10.8 - 24.14 16.66 37.77 - 16.66 - 37.77 1.4 0 23.8 55.25 - 23.8 - 55.25 10.8 24.61 - 10.8 - 24.61 16.66 38.68 - 16.66 - 38.68 1.5 0 23.8 56.55 - 23.8 - 56.55 10.8 25.08 - 10.8 - 25.08 16.66 39.59 - 16.66 - 39.59 1.6 0 23.8 57.85 - 23.8 - 57.85 10.8 25.54 - 10.8 - 25.54 16.66 40.5 - 16.66 - 40.5 1.7 0 23.8 59.15 - 23.8 - 59.15 10.8 26.01 - 10.8 - 26.01 16.66 41.41 - 16.66 - 41.41 1.8 0 60.45 - 60.45 26.48 - 26.48 42.32 - 42.32 1.9 0 61.75 - 61.75 26.95 - 26.95 43.23 - 43.23 notes: 1. based o n nominal impedance of 25 ohms (full drive) , 55 ohms (half drive) and 36 ohms ( three - quarters ) at vddq/2 2. the full variation in driver current from minimum to maximum due to process, temperature and voltage will lie within the outer bounding lines of the i - v curve. 3. the i - v current for the optional quarter drive strength is approximately 50% of the half drive strength. 4. the iv current for the three - quarters strength driver is approximately 70% of the full drive strength current. 5 . implementation and a vailability of three - quarters strength driver is optional for speed bins lpddr333 and below.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 23 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved i - v curves for full, three - quarters and half drive strength characteristics are specified under best and worst process variation/conditions - 70 - 50 - 30 - 10 10 30 50 70 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 3/4 - pd - max 3/4 - pd - min 3/4 - pu - max 3/4 - pu - min full - pd - max full - pd - min full - pu - max full - pu - min half - pd - max half - pd - min half - pu - max half - pu - min
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 24 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved basic functionali ty the lpddr sdram is a high - speed cmos, dynamic random access memory internally configured as a four - bank dram. the double data rate architecture is essentially a 2n prefetch with an interface designed to transfer two data words per cloc k cycle at the i/o pins. a single read or write access for the lpddr sdram effectively consists of a single 2n - bit wide, one clock cycle data transfer at the internal dram core and two corresponding n - bit wide, one - half - clock - cycle data transfers at the i/o pins. read and w rite access to the lpddr sdram are burst oriented; access start at a selected location and continue for a programmed number of locations in a programmed sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be activated (ba0 - ba1 select the bank; a0 - a1 3 select the row). the address bits registered coinci dent with the read or write comman d are used to select the bank and the starting column location for the burst operation. the mobile ddr sdram provides for programmable read or write burst lengths of 2, 4, 8, or 16. an auto precharge function may be enabled to provide a self - timed row prec harge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of the mobile ddr sdrams supports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activa tion time. an auto refresh mode is provided, along with a power saving power - down mode. deep power - down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. data will not be retained after device enters deep powe r - down mode. two self refresh features, temperature - compensated self refresh (tcsr) and partial array self refresh (pasr), offer additional power saving. tcsr is controlled by the automatic on - chip temperature sensor. the pasr can be customized using the e xtended mode register settings. the two features may be combined to achieve even greater power saving. the dll that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal opera tion, the lpddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. initialization lpddr sdrams must be powered up and initialized i n a predefined manner. operations procedures other than those specified may result in undefined operation. if there is any interruption to the device power, the initialization routine should be followed. the steps to be followed for device initialization a re listed below. . the mode register and extended mode register do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecified operation. the clock stop feature is not available until the device has be en properly initialized from steps 1 through 11.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 25 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved the following sequence is required for power up and initialization 1. provide power, the device core power (vdd) and the device i/o power (vddq) must be brought up simultaneously to prevent device latch - up. although not required, it is recommended that vdd and vddq are from the same power source. also assert and hold clock enable (cke) to a lv - cmos logic high level 2. once the system has established consistent device power and cke is driven high, it is safe to apply stable clock 3. there must be at least 200 s of valid clocks before any command may be given to the dram. during this time nop or deselect commands must be issued on the command bus. 4. issue a precharge all command. 5. provide nops or deselect commands for at least trp time. 6. issue an auto refresh command followed by nops or deselect command for at least trfc time. issue the second auto refresh command followed by nops or deselect command for at least trfc time. note as part of the initialization sequence there must b e two auto refresh commands issued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. 7. using the mrs command, load the base mode register. set the desired operating modes. 8. provide nops or deselect comman ds for at least tmrd time. 9. using the mrs command, program the extended mode register for the desired operating modes. note the order of the base and extended mode register programming is not important. 10. provide nop or deselct commands for at least tm rd time. 11. the dram has been properly initialized and is ready for any valid command. brief description of initialization sequence step description for initialization 1 vdd and vddq ramp: cke must be held high 2 apply stable clocks 3 wait at least 20 0 s with nop or deselect on command bus 4 precharge all 5 assert nop or deselct for trp time 6 issue two autorefresh commands each followed by nop or deselect commands for trfc time 7 configure mode register 8 assert nop or deselect for tmrd time 9 configure extended mode register 10 assert nop or deselect for tmrd time 11 lpddr sdram is ready for any valid command
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 26 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved initialization sequence diagram n otes: 1. pre = precharge command; lmr = load mode register command; ar = auto refresh command; ac t = active command. 2. nop or deselect commands are required for at least 200us. 3. other valid commands are possible. 4. nops or deselects are required during this time.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 27 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved initialization sequence with temperature o utput signal (unsupported on packag e level) tq signal initialization during device initialization the tq signal output will be invalid until ttq after the first mrs command. following ttq the tq signal will output logic - high when the device temperature is greater than, or equal to, 85 o c , an d logic - low when the device temperature is less than 85 o c . there is no high - impedance state for this output signal. temperature output signal the lpddr - sdram device may include an optional temperature output signal (tq). this signal is an asynchronous lvcm os output which outputs a logic - high when the device temperature is greater than, or equal to, 85 o c and a logic - low when the device temperature is less than 85 o c. there is no high - impedance state output from this signal. the tq output signal activates even during clock stop, power down, and self refresh modes. the signal is not valid during initialization and becomes valid after ttq following the first mrs command. when tq output is logic - high, tref is specified to be 16ms. additionally, ac parameters shall be de - rated to 20% and dc parameters shall not be guaranteed.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 28 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved register definition mode registers and extended mode registers the mode registers are used to define the specific mode of operation of the lpddr sdram. this define includes the definition of a burst length, a burst type, a cas latency. additionally, driver strength, temperature compensated self refresh (tcsr), and partial array self refresh (pasr) are also user defined variables and must be programmed with an extended mode register set (emrs) command. the default value of the mode register is not defined, therefore the mode register must be written after power up for proper operation. the mode register must be loaded when all banks are idle and no bursts are progress, and the controller must w ait the specific time t mrd before initiating any subsequent operation. violating either of these requirements will result in unspecified operation. the mrs contents wont be changed until it is reprogrammed, the device goes into deep power - down, or the dev ice loses power. the mode register is written by asserting low on ?s , ras , ?as , we , ba0 and ba1, while controlling the state of address pins a0~a1 3 . the mode register contents can be changed using the same command and clock cycle requirements during norma l operation as long as all banks are in the precharge state. the mode register is divided into various fields depending on the functionality. burst length is defined by a0~a2 with options of 2, 4, 8 and 16 bit burst length. burst address sequence type is d efined by a3 and cas latency is defined by a4~a6. a7~a1 3 must be set to low to ensure future compatibility. standard mode register definition n ote 1 : a logic 0 should be programmed to all unused / undefined address bits to ensure future compatibil ity. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 bt ba1 ba0 a3 0 0 0 0 1 1 1 0 1 1 a6 a5 a4 a2 a1 a0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 a8 a7 0 0 - - normal operation all other states reserved operating mode mr select standard mr status register extended mr reserved a13-a9 0 operating mode cas latency - reserved reserved reserved reserved 8 16 reserved 3 reserved reserved reserved 2 4 reserved reserved 2 sequential interleaved bl mr select cas latency bl burst type
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 29 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved burst length, type, and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as above figure. the ordering of access within a burst is determined by the burst length, burst ty pe, and the starting column address. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. the burst length is defined by bits a0 C a2. burst length options include 2, 4, 8 or 16 for both t he sequential and the interleaved burst types. when a read or write command is issued, a block of columns equal to the bl is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap when a boundary is reached. the block is uniquely selected by a1 C ai when bl = 2, by a2 C ai when bl = 4, by a3 C ai when bl = 8, and by a4 C ai when bl = 16 ( where ai is the most significant column address bit for a given configuration ) . the remaining (least significant) address bits are used to specify the starting location within the block. the programmed bl applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved via the standard mode register. burst type and burst order burst length starting column address burst t ype a3 a2 a1 a0 sequential interleaved 2 - - - 0 0,1 0,1 - - - 1 1,0 1,0 4 - - 0 0 0,1,2,3 0,1,2,3 - - 0 1 1,2,3,0 1,0,3,2 - - 1 0 2,3,0,1 2,3,0,1 - - 1 1 3,0,1,2 3,2,1,0 8 - 0 0 0 0,1, 2,3,4,5,6,7 0,1,2,3,4,5,6,7 - 0 0 1 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 - 0 1 0 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 - 0 1 1 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 - 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 - 1 0 1 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 - 1 1 0 6,7,0,1, 2,3,4,5 6,7,4,5,2,3,0,1 - 1 1 1 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 16 0 0 0 0 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f 0 0 0 1 1,2,3,4,5,6,7,8,9,a,b,c,d,e,f,0 1,0,3,2,5,4,7,6,9,8,b,a,d,c,f,e 0 0 1 0 2,3,4,5,6,7,8,9,a,b,c,d,e,f,0, 1 2,3,0,1,6,7,4,5,a,b,8,9,e,f,c,d 0 0 1 1 3,4,5,6,7,8,9,a,b,c,d,e,f,0,1,2 3,2,1,0,7,6,5,4,b,a,9,8,f,e,d,c 0 1 0 0 4,5,6,7,8,9,a,b,c,d,e,f,0,1,2,3 4,5,6,7,0,1,2,3,c,d,e,f,8,9,a,b 0 1 0 1 5,6,7,8,9,a,b,c,d,e,f,0,1,2,3,4 5,4,7,6,1,0,3,2,d,c,f,e,9,8,b,a 0 1 1 0 6,7,8,9,a,b,c,d,e,f,0,1,2,3,4,5 6,7,4,5,2,3,0,1,e,f,c,d,a,b,8,9 0 1 1 1 7,8,9,a,b,c,d,e,f,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0,f,e,d,c,b,a,9,8 1 0 0 0 8,9,a,b,c,d,e,f,0,1,2,3,4,5,6,7 8,9,a,b,c,d,e,f,0,1,2,3,4,5,6,7 1 0 0 1 9,a,b,c,d,e,f,0,1,2,3,4, 5,6,7,8 9,8,b,a,d,c,f,e,1,0,3,2,5,4,7,6 1 0 1 0 a,b,c,d,e,f,0,1,2,3,4,5,6,7,8,9 a,b,8,9,e,f,c,d,2,3,0,1,6,7,4,5 1 0 1 1 b,c,d,e,f,0,1,2,3,4,5,6,7,8,9,a b,a,9,8,f,e,d,c,3,2,1,0,7,6,5,4 1 1 0 0 c,d,e,f,0,1,2,3,4,5,6,7,8,9,a,b c,d,e,f,8,9,a,b,4,5,6,7,0, 1,2,3 1 1 0 1 d,e,f,0,1,2,3,4,5,6,7,8,9,a,b,c d,c,f,e,,9,8,b,a,5,4,7,6,1,0,3,2 1 1 1 0 e,f,0,1,2,3,4,5,6,7,8,9,a,b,c,d e,f,c,d,a,b,8,9,6,7,4,5,2,3,0,1 1 1 1 1 f,0,1,2,3,4,5,6,7,8,9,a,b,c,d,e f,e,d,c,b,a,9,8,7,6,5,4,3,2,1,0
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 30 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved cas latency (cl) the cas latency, or read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. cas latency is defined by bit a6~a4 in the standard mode register. if a read command is registered at a clock edge n, and the cas latency is 3 clocks, the first data element will be valid at (n + 2 t ck + t ac). if a read command is registered at a clock edge n, and the cas latency is 2 clocks, the first data element will be valid at (n + 1 t ck + t ac). exten ded mode register definition the extended mode register controls functions beyond those controlled by the mode register; these additional functions include output drive strength selection, temperature compensated self refresh (tcsr) and partial array self refresh (pasr). tcsr and pasr are effective in self refresh mode only. the extended mode register is programmed via the load mode register command with ba0=0 and ba1=1, and the information wont be changed until it is reprogrammed, the device goes into dee p power - down mode, or the device loses power. the emrs must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent operation. violating either of these requirem ents will result in unspecified operation. address bits a0 - a2 specify pasr, a3 - a4 the tcsr, a5 - a6 the drive strength. a logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 31 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved temperature compensated self refresh ( tcsr) on this version of the lpddr sdram, the internal temperature sensor is implemented to adjust the self refresh oscillator automatically base on the case temperature. to maintain backward compatibility, the programming of tcsr bits no effect on the dev ice so t he address bits, a3 and a4 are ignore d (dont care) during emrs programming. partial - array self refresh (pasr) for further power savings during self refresh, the pasr feature may allow the self refresh to be restr icted to a variable portion of the total array. they are full array (default: banks 0, 1, 2, and 3), 1/2 array (banks 0 and 1) and 1/4 array (bank 0). data outside the defined area will be lost. address bits a0 to a2 are used to set pasr. output drive strength lpddr sdram provides the optio n to control the drive strength of the output buffers for the smaller systems or point - to - point environments. the value was selected based on the expected loading of the memory bus. total four values provided, and they are 25 ohm, 36ohm, 55ohm, and 80ohm i nternal impedance. they are full, three - quarter, one - half, and one - quarter drive strengths, respectively. extended mode register n ote 1: on - die temperature sensor is used in place of tcsr. setting these bits will have no effect. n ote 2: a logic 0 shoul d be programmed to all unused / undefined address bits to ensure future compatibility. n ote 3: implementation and availability of three - quarters strength driver is optional for speed bins lpddr333 and below. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 a7 a6 a5 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 0 a2 a1 a0 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 a8 0 - - all other states reserved reserved reserved reserved a13-a9 operating mode 0 normal operation reserved half array(ba1=0) reserved 1/4 array(ba1=ba0=0) reserved reserved reserved three-quarters three-quarters pasr reserved all banks standard mr full status register half extended mr quarter mr select operating mode ds tcsr 1 pasr mr select driver strength
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 32 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved status read register (srr) the status read reg ister (srr) is only for read, and contains the specific die information such as density, device type, data bus width, refresh rate, revision id and manufactures. the srr is read via the load mode register command with ba0=1 and ba1=0. the sequence to perfo rm an srr command is as follows: ? the device had been properly initialized and in the idle or all banks precharge state. ? issue a lmr command with ba [1:0] = 01. ? wait t srr; only nop or deselect commands are supported during this period. ? issue a read comman d with all address pins set to 0. ? cas latency cycles later, the device returns the registers data. the srr read with fixed burst length 2, first bit of the bur st output srr data, and second bit of the burst is dont care. ? the next command to the sdram must be issued t src after the srr read command is issued; only nop or deselect commands are supported during this period. notes: 1. srr can only be issued after power - up sequence is complete, and all banks are precharged and in the idle state. 2. nop or desel ect commands are required between lmr and read command (tsrr) and between read and next valid command (tsrc) 3. cas latency is predetermined by the programming of the mode register. here cl=3 as an example only. 4. burst length is fixed to 2 for srr regardless o f the value programmed by the mode register. 5. the second bit of the data - out burst is a dont care.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 33 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved register definition status register definition notes: 1. reserved bits should be set to zero for future compatibility. 2. refresh multiplier is based on the memory devices on - board temperature sensor. required average periodic refresh interval = trefi x multiplier.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 34 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved lpddr sdram command description and operation command truth table nane (function) abbr . ?s ? ras ? ?as ? we ? ba a10/ap addr notes deselect deselect h x x x x x x 2 no operation nop l h h h x x x 2 active (select bank and active row) act l l h h valid row row read (select bank, column, and start read burst) read l h l h valid l col read with ap (read burst with auto precharge) reada l h l h valid h col 3 write (select bank, column, and start write burst) write l h l l valid l col write with ap (write burst with auto precharge) writea l h l l valid h col 3 burst terminate or enter deep power - down bst l h h l x x x 4,5 precharge (deactive row i n selected bank) pre l l h l valid l x 6 precharge all (deactive rows in all banks) preall l l h l x h x 6 auto refresh or enter self refresh refa / refs l l l h x x x 7,8,9 load mode register lmr l l l l valid op - code 10 notes: 1. all states and seque nces not shown are illegal or reserved. 2. deselect and nop are functionally interchangeable. 3. autoprecharge is non - persistent. a10 high enables auto precharge, while a10 low disables autoprecharge 4. burst terminate applies to only read bursts with auto precharge disabled. this command is undefined and should not be used for read with auto precharge enabled, and for write bursts. 5. this command is burst terminate if cke is high and deep power down entry if cke is low. 6. if a10 is low, bank address dete rmines which bank is to be precharged. if a10 is high, all banks are precharged and ba0 - ba1are dont care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are don't care except for cke. intern al refresh counters control bank and row addressing. 9. all banks must be precharged before issuing an auto - refresh or self refresh command. 10.ba0 and ba1 value select between mrs and emrs. 11.cke is high for all commands shown except self refresh and dee p power - down.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 35 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved dm operation truth table function dm dq notes write enable l valid 1,2 write inhibit h x 1,2 notes: 1. used to mask write data, provided coincident with the corresponding data. 2. all states and sequences not shown are reserved and/or illegal .
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 36 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved cke truth table current state cke command (n) ras , ?as , we , ?s action (n) - result notes cke n - 1 cke n power down l l x maintain power down self refresh l l x maintain self refresh deep power down l l x maintain deep power down power down l h nop or deselect exit power down 5, 6, 9 self refresh l h nop or deselect exit self refresh 5, 7, 10 deep power down l h nop or deselect exit deep power down 5, 8 all banks idle h l nop or deselect precharge power down entry 5 bank(s) active h l no p or deselect active power down entry 5 all banks idle h l auto refresh self refresh entry all banks idle h l burst terminate deep power down entry see the other truth tables h h see the other truth tables notes: 1. cken is the logic state of cke at clock edge n; cken - 1 was the state of cke at the previous clock edge. 2. current state is the state of lpddr immediately prior to clock edge n. 3. commandn is the command registered at clock edge n, and actionn is the result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. deselect and nop are functionally interchangeable. 6. power down exit time (txp) should elapse before a command other than nop or deselect is issued. 7. self refresh exit time (txsr) should elapse before a co mmand other than nop or deselect is issued. 8. the deep power - down exit procedure must be followed as discussed in the deep power - down section of the functional description. 9. the clock must toggle at least once during the txp period. 10.the clock must to ggle at least once during the txsr time. basic timing parameters for commands note 1: input = a0 C an, ba0, ba1, cke, ?s , ras , ?as , we ; an = address bus msb.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 37 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved current state bank n truth table (command to bank n) current state command action (n) - result notes ?s ? ras ? ?as ? we ? description any h x x x deselect (nop) continue previous operation l h h h nop continue previ ous operation idle l l h h active select and active row l l l h auto refresh auto refresh 10 l l l l mode register set mode register set 10 row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactive row in bank or banks 4 read (ap disable) l h l h read select column & start new read burst 5,6 l h l l write select column & start write burst 5,6,13 l l h l precharge truncate read burst, start precharge l h h l burs t terminte burst terminate 11 write (ap disable) l h l h read select column & start read burst 5,6,12 l h l l write select column & start new write burst 5,6 l l h l precharge truncate write burst, start precharge 12 notes: 1. the table applies when both cken - 1 and cken are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. this command ma y or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. 5. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 6. the new read o r write command could be auto precharge enabled or auto precharge disabled. 7. current state definitions: - idle: the bank has been precharged, and trp has been met. - row active: a row in the bank has been activated, and trcd has been met. no data bursts / ac cesses and no register accesses are in progress. - read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. - write: a write burst has been initiated, with auto precharge disabled, and has not yet term inated or been terminated. 8. the following states must not be interrupted by a command issued to the same bank. deselect or nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable co mmands to the other bank are determined by its current state and truth table - current state bank n - command to bank n/m. - precharging: starts with the registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the i dle state. - row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be i n the row active state.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 38 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved - read with ap enabled: starts with the registration of the read command with auto precharge ena bled and ends when trp has been met. once trp has been met, the bank will be in the idle state. - write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. 9. the following states must not be interrupted by any executable command; deselect or nop commands must be applied to each positive clock edge during these states. - refreshing: starts with registration of an auto refresh command and end s when trfc is met. once trfc is met, the device will be in an all banks idle state. - accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the device will be in an all banks i dle state. - precharging all: starts with the registration of a precharge all command and ends when trp is met. once trp is met, the bank will be in the idle state. 10.not bank - specific; requires that all banks are idle and no bursts are in progress. 11.not bank - specific. burst terminate affects the most recent read burst, regardless of bank. 12.requires appropriate dm masking. 13.a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 39 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved current state bank n truth table (command to bank m) current state command action (n) - result notes ?s ? ras ? ?as ? we ? description any h x x x deselect (nop) continue previous operation l h h h nop continue previous operation idle x x x x any any command allowed to bank m row activating, active, or precharging l l h h active select and activate row l h l h read select column & start read burst 8 l h l l write select column & start write burst 8 l l h l precharge precharge read (ap disable) l l h h active select and activate row l h l h read select column & start read burst 8 l h l l w rite select column & start write burst 8,10 l l h l precharge precharge write (ap disable) l l h h active select and activate row l h l h read select column & start read burst 8,9 l h l l write select column & start write burst 8 l l h l precha rge precharge read (ap enabled) l l h h active select and activate row l h l h read select column & start read burst 5,8 l h l l write select column & start write burst 5,8,10 l l h l precharge precharge write (ap enabled) l l h h active selec t and activate row l h l h read select column & start read burst 5,8 l h l l write select column & start write burst 5,8 l l h l precharge precharge notes: 1. the table applies when both cken - 1 and cken are high, and after txsr or txp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeable. 3. all states and sequences not shown are illegal or reserved. 4. current state definitions: - idle: the bank has been precharged, and trp has been m et. - row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register accesses are in progress. - read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminate d. - write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 40 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved 5. read with ap enabled and write with ap enabled: the read with auto precharge enabled or write with auto precharge enabled states can b e broken into two parts: the access period and the precharge period. for read with ap, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with ap, the precharge period begins when twr ends, with twr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or trp) be gins. during the precharge period of the read with ap enabled or write with ap enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in either case, all other related limitations apply (e.g. contention between read data and write data must be avoided). from command to command min. delay (w/ concurrent auto precharge) write w/ ap read or read w/ ap write or write w/ ap pre charge active [1 + (bl/2)] tck + twtr (bl/2) tck 1 tck 1 tck read w/ ap read or read w/ ap write or write w/ ap precharge active (bl/2) tck [cl + (bl/2)] tck 1 tck 1 tck 6. auto refresh, self refresh, and mode register set commands may only be issued whe n all bank are idle. 7. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 8. reads or writes listed in the command column include reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. requires appropriate dm masking. 10.a write command may be applied after the completion of data output, otherwise a burst terminate command must be issued to end the read prior to asserting a write command.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 41 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved command no operation (nop) the no operation (nop) command is used to instruct the selected lpddr sdram to perform a nop. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. des elect the deselect function ( ?s =high) prevents new commands from being executed by the lpddr sdram. operations already in progress are not affected. load mode register the mode registers are loaded via the address inputs and can only be issued when all banks are idle, no bursts are i n progress. the subsequent executable command can not be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for subsequent access. the values on the ba0 and ba1 inputs select the bank, and the ad dresses provided on inputs a0 - a1 3 selects the row. once a row is open, a read or write command could be issued to that row, subject to the t rcd specification. a subsequent active command to another row in the same bank can only be issued after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defined by t rc. the subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of t otal row - access overhead. the minimum time interval between two successive active commands on different banks is defined by t rrd. these rows remain active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 42 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read the read command is used to initiate a burst read access to an active row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the star ting column location. the value of a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. during read bursts, dqs is driven by the lpddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data - out element is known as the read postamble. the fi rst data - out element is edge aligned with the first rising edge of dqs and the successive data - out elements are edge aligned to successive edges of dqs.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 43 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved write the write command is used to initiate a burst write access to an active row, with a burst len gth as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be prech arged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. during write burst s, the first valid data - in element will be registered on the first rising edge of dqs following the write command, and the subsequent data elements will be registered on successive edges of dqs. the low state of dqs between the write command and the first rising edge is called the write preamble; the low state on dqs following the last data - in element is called write postamble.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 44 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank (s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged. in case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued. a precharge command will be treated as a nop if there is no open row in t hat bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. this i s accomplished by using a10 (a10 = high), to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank / row that is addressed with the read or write command is automatically performed upon completion of the read o r write burst. auto precharge is non persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. the user must not issue ano ther command to the same bank until the precharging time (trp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this specification. burst terminate the burst terminate command is used to truncate read bursts with auto precharge disabled. the most recently registered read command prior to the burst terminate command will be truncated. the burst terminate command is not bank specific, and should not be used to terminate write bursts.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 45 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved refresh lpddr sdram devices require a refresh of all rows in any rolling 64ms interval. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed even t in self refresh mode: - auto refresh auto refresh command is used during normal operation of the lpddr sdram, and its non - persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh contr oller. the address bits become dont care during auto refresh. the lpddr sdram requires auto refresh commands at an average periodic interval of t refi. to provide improved efficiency in scheduling and switching between tasks, some flexibility in the abso lute interval is provided. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. - self refresh self refresh command can be used to retain data in the lpddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the lpddr sdram retains data without external clocking. the lpddr sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is initiated like an auto refresh command, except cke is low . input signals except cke are dont care during self refresh. the user may halt the external clock one clock after the self refresh command is registered.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 46 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved once the self refresh command is registered, the external clock can be halted after one clock la ter. cke must be held low to keep the device in self refresh mode, and internal clock also disabled to save power. the minimum time that the device must remain in self refresh mode is t rfc. in the self refresh mode, two additional power - saving options exi st: temperature compensated self refresh and partial array self refresh. during this mode, the device is refreshed as identified in the extended mode register. an internal temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring data integrity. during self refresh operation, refresh intervals are scheduled internally and may vary. these refresh intervals may be different then the specified t refi time. for this reason, the self refresh command must not be used as a substitute for the auto refresh command. the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. when cke is high, the lpddr sdram must have nop commands issued for t xsr time. the use o f self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 47 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved power - down power - down is e ntered when cke is registered low (no accesses can be in progress). if power - down occurs when all banks are idle, this mode is referred to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as act ive power - down. power - down mode deactivates the input and output buffers, excluding ck, ?? and cke. cke keep low to maintain device in the power - down mode, and all other inputs signals are dont care. the minimum power - down duration is specified by t cke. the device can not stay in this mode for longer than the refresh requirements of the device, without losing data. the power - down state is synchronously existed when cke is registered high (along with a nop or deselect command). a valid command can be issu ed after t xp after exist from power - down.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 48 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved deep - power - down the deep power - down (dpd) mode enables very low standby currents. all internal voltage generators inside the lpddr sdram are stopped and all memory data is lost in this mode. all the informati on in the mode register and the extended mode register is lost. deep power - down is entered using the burst terminate command except that cke is registered low. all banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this state, cke must be held in a constant low state. to exit the dpd mode, cke is taken high after the clock is stable and nop commands must be maintained for at least 200 s. after 200 s a complete re - initialization is required following steps 4 through 11 as defined for the initialization sequence.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 49 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved clock stop stopping a clock during idle periods is an effective method of reducing power consumption. the lpddr sdram sup ports clock stop mode under the following conditions: ? the last command (active, read, write, precharge, auto refresh or mode register set) has executed to completion, including any data - out during read bursts; the number of clock pluses per access command depends on the devices ac timing parameters and the clock frequency; ? the related timing condition ( t rcd, t wr, t rp, t rfc, t mrd) has been met; ? cke is held high. when all conditions have been met, the device is either in idle state or row active state, a nd clock stop may be entered with ck held low and ?? held high. clock stop mode is exited by restarting the clock. at least one nop command has to be issued before the next access command may be applied. additional clock pulses might be required depending on the system characteristics. c lock stop mode entry and exit : ? initially the device is in clock stop mode ? the clock is restarted with the rising edge of t0 and a nop on the command inputs ? with t1 a valid access command is latched; this command is followed by nop commands in order to allow for ? clock stop as soon as this access command is completed ? tn is the last clock pulse required by the access command latched with t1 ? the clock can be stopped after tn
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 50 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved timing reads read burst operations are initiated wit h a read command. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. during read bursts, the valid data - out element from the starting column address will be available following the cas latency after the read command. the first data - out element is edge aligned with the first rising edge of dqs and the successive data - out elements are edge aligned to successive edges of dqs. dqs is driven by lpddr sdram along with output data. upon completion of a read burst, assuming no other read command has been initiated, the dq will go to high - z. read burst operation (bl=4, and cl=2, cl=3) notes: 1. dout n = data - out from column n. 2. shown with nominal tac, tdqsck, and tdqsq.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 51 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved data output timing C t ac and t dqsck notes: 1. dq transitioning after dqs transitions define t dqsq window. 2. all dq must transition by t dqsq after dqs transit ions, regardless of t ac. 3. t ac is the dq output window relative to ck and is the long - term component of dq skew. 4. commands other than nop may be valid during this cycle.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 52 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved data output timing C t dqsq, t qh and data valid window (x32) notes: 1. dq transitionin g after dqs transitions define t dqsq window. 2. byte 0 is dq0 - dq7, byte 1 is dq8 - dq15, byte 2 is dq16 - dq23, and byte 3 is dq24 - dq31. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition . 4. t oh is derived from t hp, t oh = t hp C t ohs. 5. t oh is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived from each dqs transition and is t oh C t dqsq. 7. dq[7:0] and dqs0 for byte 0; dq[15:8] and dqs1 for byte 1; dq[23:16] and dqs2 for byte 2; dq[31:24] and dqs3 for byte 3.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 53 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved data output timing C t dqsq, t qh and data valid window (x16) notes: 1. dq transitioning after dqs transitions define t dqsq window. ldqs defines the lower by te and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition . 4. t oh is derived from t hp, t oh = t hp C t ohs. 5. t oh is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived from each dqs transition and is t oh C t dqsq. 7. dq9, dq9, dq10, dq11, dq12, dq13, dq14, or dq15.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 54 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read to read data from a read burst may be concatenated or truncated by a subsequent read command. the first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being trunca ted. the new read command should be issued x cycles after the first read command, where x equals the number of desired data - out element pairs (pairs are required by the 2n prefetch architecture). consecutive read bursts (cl=2 and cl=3) notes: 1. dout n (or b) = data - out from column n (or column b). 2. bl = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 55 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved nonconsecutive read bursts (cl=2 and cl=3) notes: 1. dout n (or b) = data - out from column n ( or column b). 2. bl = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. shown with nominal t ac, t dqsck, and t dqsq.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 56 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved random read bursts (cl=2 and cl=3) notes: 1. dout n (or x, b, g) = data - out from column n ( or column x, column b, column g). 2. bl = 2, 4, 8, or 16 (if 4, 8 or 16, the following burst interrupts the previous). 3. shown with nominal t ac, t dqsck, and t dqsq.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 57 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read burst terminate data from any read burst may be truncated with a burst terminate command. the burst terminate latency is equal to read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command where x equals the desired data - out element pairs (pairs are required by the 2n - prefetech architecture). termi nating a read bursts (cl=2 and cl=3) notes: 1. dout n = data - out from column n. 2. bl = 4, 8, or 16. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. bst = burst terminate command; page remains open. 5. cke = high.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 58 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read to write data from read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used. read to write (cl=2 and cl=3) notes: 1. dout n = data - out from column n. 2. bl = 4, 8, or 16. 3. shown with nominal t ac, t dqsck , and t dqsq. 4. bst = burst terminate command; page remains open. 5. cke = high.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 59 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read to precharge a read burst may be followed by, or truncated with, a precharge command to the same bank. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs. following the precharge command, a subsequent command to the same bank can not be issued until t rp is met. part of the row precharge time is hidden during the access of the last data element. in the case of a read being executed to completion, a precharge command issued at optimum time provides the same operation as read with ap. the disadvantage of precharge command is that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that can be used to truncate bursts.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 60 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved read to precharge (cl=2 and cl=3) notes: 1. dout n = data - out from column n. 2. bl = 4, or an interrupted burst 8 or 16. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. read - to - precharge equals 2 clocks, which enables 2 data pairs of data - out. a read command with auto precharge enabled, provided t ras (min) is met, would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl/2. 5. p re = precharge command; act = active command.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 61 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved writes write burst operations are initiated with a write command. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that burst acc ess. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. during write bursts, the first valid data - in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. input data appearing on the data bus is written to the memory array subject to the state of the data mask dm inputs coincident with the data. write C dm operation (cl=2 and cl=3) notes: 1. din n = d ata - in from column n. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. bank x at t8 is dont care, if a10 is high at t8. 5. pre = precharge command. 6. nop commands are shown for ease of illustration; other commands may be valid at these time.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 62 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved write burst t he time between the write command and the first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75% to 125% of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases (that is, t dqss(min) and t dqss(max)) might not be intuitive, they have also been included. upon completion of the burst, assuming no other commands have been initiated, the dqs will remain high - z and any additional input data will be ignored. write burst (no minal, t dqss(min)/(max), bl=4) notes: 1. din b = data - in from column b. 2. an uninterrupted burst of 4 is shown. 3. a10 is low with the write command (auto precharge is disabled).
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 63 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved write to write data for any write burst may be concatenated with or truncated by a subsequent write command. in either case, a continuous flow input data can be maintained. the new write command can be issued on any positive edge of the clock following the previous write command. the first data - in element from the new burst is applied af ter either the last element of a completed burst or the last desired data element of the longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data - in elem ent pairs (pairs are required by the 2n - prefetch architecture). consecutive write - to - write (bl=4) notes: 1. din b (n) = data - in from column b (n). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 64 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved nonconsecutive write - to - w rite (bl=4) notes: 1. din b (n) = data - in from column b (n). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 65 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved random write cycles notes: 1. din b (or x, n, a, g) = data - in from column b (or x, n, a, g). 2. b (or x, n, a, g) = the next data - in following din b (x, n, a, g) according to the programmed burst order. 3. programmed bl = 2, 4, 8, or 16 in cases shown. 4. each write command may be to any bank.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 66 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved write to read data for any write burst may be followed by a subsequent read comma nd. to follow a write without truncating the write burst, t wtr should be met as shown in figure. non - interrupting write - to - read (nominal, t dqss(min)/(max), bl=4) notes: 1. din b = data - in from column b; dout n = data - out for column n. 2. an uninterrupted bur st of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last data - in pair. 4. the read and write commands are to the same device. however, the read and write commands may be to different devices. in which case t wtr is not required and t he read command could be applied earlier. 5. a10 is low with the write command (auto precharge is disabled).
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 67 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved data for any write burst may be truncated by a subsequent read command as shown in figure. note that the only data - in pairs that are registered prio r to the t wtr period are written to the internal array, and any subsequent data - in must be masked with dm. interrupting write - to - read (nominal, t dqss(min)/(max), bl=4) notes: 1. din b = data - in from column b; dout n = data - out for column n. 2. an uninterrupt ed burst of 4 is shown; two data elements are written. 3. t wtr is referenced from the first positive ck edge after the last data - in pair. 4. a10 is low with the write command (auto precharge is disabled). 5. dqs is required at t2 and t2n (nominal case) to register dm.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 68 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved write to precharge data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, twr should be met. non - interrupting write - to - precharge (nominal, t dqss(min)/(max), bl=4) notes: 1. p re = precharge. 2. din b = data - in from column b. 3. an uninterrupted burst of 4 is shown. 4. a10 is low with the write command (auto precharge is disabled). 5. t wtr is referenced from the first positive ck edge after the last data - in pair. 6. the precharge and write com mands are to the same device. however, the precharge and write commands can be to different devices; in this case, t wr is not required and the precharge command can be applied earlier.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 69 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved data for any write burst may be truncated by a subsequent precharge command as shown in figure. note that the only data - in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data - in must be masked with dm. after the precharge command, a subsequent command to the same ba nk can not be issued until t rp is met. interrupting write - to - precharge (nominal, t dqss(min)/(max), bl=8) notes: 1. pre = precharge. 2. t wr is referenced from the first positive ck edge after the last data - in pair. 3. din b = data - in from column b. 4. an interrupte d burst of 8 is shown; two data elements are written. 5. a10 is low with the write command (auto precharge is disabled). 6. dqs is required at t4 and t4n to register dm.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 70 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged. in case where only one bank is to be precharged (a10=low), inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a pre charg e command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual bank precharge fu nction described previously, but without requiring an explicit command. this is accomplished by using a10 (a10=high), to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank / row that is addressed with the re ad or write command is automatically performed upon completion of the read or write burst. auto precharge is non - persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that a precharge is initi ated at the earliest valid stage within a burst. the earliest valid stage is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras(min). the read with auto precharge enabled or write with auto pre charge enabled states can each be broken into two parts: the access period and the precharge period. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. in addition, during a write with auto precharge, at least one clockis required during t wr time. during the prechare period, the user must not issue another command to the same bank until t rp is satisfied. this device supports t ras lock - out. in the case of a single read with auto - precharge or a single write with auto - precharge issued at t rcd(min), the internal precharge will be delayed until t ras(min) has been satisfied. concurrent auto precharg e this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read or write data tr ansfer already in process. this feature enables the precharge to complete in the bank in which the read or write with auto precharge was executed, without requiring an explicit preachrge command, thus freeing the command bus for operations in other banks. during the access period of a read or a write with auto precharge, only active and precharge commands may be applied to other banks. during the precharge period, active, precharge, read, and write commands may be applied to other banks. in either situation , all other related limitations apply.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 71 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved bank read with auto precharge ( t ac, t dqsck(min)/(max), bl=4) notes: 1. din n = data - out from column n. 2. bl =4 in the case shown. 3. enable auto precharge. 4. nop commands are shown for ease of illustration; other command s may be valid at these times.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 72 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved bank read without auto precharge ( t ac, t dqsck(min)/(max), bl=4) notes: 1. din n = data - out from column n. 2. bl =4 in the case shown. 3. disable auto precharge. 4. bank x at t5 is dont care, if a10 is high at t5. 5. pre = precharge . 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7. the precharge command can only be applied at t5, if t ras(min) is met.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 73 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved bank write with auto precharge (bl=4) notes: 1. din n = data - out from column n. 2. bl =4 in the case shown. 3. enable auto precharge. 4. nop commands are shown for ease of illustration; other commands may be valid at these times.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 74 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved bank write without auto precharge (bl=4) notes: 1. din n = data - out from column n. 2. bl =4 in the case shown. 3. disable auto p recharge. 4. bank x at t8 is dont care, if a10 is high at t8. 5. pre = precharge. 6. nop commands are shown for ease of illustration; other commands may be valid at these times.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 75 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved auto refresh auto refresh command is used during normal operation of the lpddr sdr am, and is analogous to ?as - before - ras (cbr) refresh in the fpm/edo drams. the auto refresh is non - persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. the address bits be come dont care during auto refresh. the lpddr sdram requires auto refresh commands at an average periodic interval of t refi. to provide improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is p rovided. although it is not a jedec requirement, cke must be active (high) during the auto refresh period to provide support for future functional features. the auto refresh period begins when the auto refresh command is registered and ends t rfc later. n otes: 1. pre = precharge; ar = auto refresh. 2. nop commands are shown for ease of illustration; other commands may be valid at these times. cke must be active during clock positive transitions. 3. nop or command inhibit are the only commands supported until after t rfc time; cke must be active during clock positive transitions. 4. bank x at t1 is dont care, if a10 is high at this point; a10 must be high if more than one bank is active. 5. dm, dq, and dqs signals are all dont care, high - z for operations shown. 6. the s econd auto precharge is not required and is only shown as an example of two back - to - back auto refresh commands.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 76 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved self refresh self refresh command can be used to retain data in the lpddr sdram, even if the rest of the system is powered down. when in the s elf refresh mode, the lpddr sdram retains data without external clocking. the lpddr sdram device has a built - in timer to accommodate self refresh operation. the self refresh command is initiated like an auto refresh command, except cke is low. input signal s except cke are dont care during self refresh. during self refresh, the device is refreshed as identified in the extended mode register. once the self refresh command is registered, the external clock can be halted after one clock later. cke must be he ld low to keep the device in self refresh mode, and internal clock also disabled to save power. the minimum time that the device must remain in self refresh mode is t rfc. in the self refresh mode, two additional power - saving options exist: temperature com pensated self refresh and partial array self refresh. during this mode, the device is refreshed as identified in the extended mode register. an internal temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring dat a integrity. during self refresh operation, refresh intervals are scheduled internally and may vary. these refresh intervals may be different then the specified t refi time. for this reason, the self refresh command must not be used as a substitute for the auto refresh command. the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. when cke is high, the lpddr sdram must have nop commands issued for t xsr time to complete any internal refr esh already in progress. notes: 1. clock must be stable, cycling within specifications by ta0, before exiting self refresh mode. 2. device must be in the all banks idle state prior to entering self refresh mode. 3. nops or deselects is required for t xsr time wi th at least two clock pulses. 4. ar = auto refresh. 5. cke must remain low to remain in self refresh.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 77 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved power - down power - down is entered when cke is registered low (no accesses can be in progress). if power - down occurs when all banks are idle, this mode is refer red to as precharge power - down; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down. power - down mode deactivates all input and output buffers, excluding ck, ?? and cke. cke keep low to maintain device in the power - down mode, and all other inputs signals are dont care. the minimum power - down duration is specified by t cke. the device can not stay in this mode for longer than the refresh requirements of the de vice, without losing data. the power - down state is synchronously existed when cke is registered high (along with a nop or deselect command). a valid command can be issued after t xp after exist from power - down. notes: 1. if this command is a precharge (or i f the device is already in the idle state), then the power - down mode shown is precharge power - down. if this command is an active (or if at least one row is already active), then the power - down mode is active power - down. 2. no column accesses can be in progres s, when power - down is entered. 3. t cke applies if cke goes low at ta2 (entering power - down); t xp applies if cke remains high at ta2 (exit power - down).
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 78 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved deep - power - down the deep power - down (dpd) mode is an operating mode used to achieve maximum power reductio n by eliminating the power of the memory array. all internal voltage generators inside the lpddr sdram are stopped and all memory data, mrs and emrs information is lost in this mode. the dpd command is the same as a burst terminate command with cke low. al l banks must be in idle state with no activity on the data bus prior to entering the dpd mode. while in this mode, cke must be held in a constant low state. to exit the dpd mode, cke is taken high after the clock is stable and nop commands must be maintain ed for at least 200us. after 200us a complete re - initialization is required. notes: 1. clock must be stable prior to cke going high. 2. dpd = deep power - down. 3. upon exit of power - down mode, a full dram initialization sequence is required.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 79 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved clock stop one me thod of controlling the power efficiency in applications is to throttle the clock that controls the lpddr sdram. the clock may be controlled in two ways: ? change the clock frequency. ? stop the clock. the lpddr sdram enables the clock to change frequency duri ng operation only if all the timing parameters are met, and all refresh requirements are satisfied. the clock can be stopped altogether if there are no dram operations in progress that would be affected by this change. any dram operation already in process must be completed before entering clock stop mode; this includes the following timings: t rcd, t rp, t rfc, t mrd, t wr, and t rpst. in addition, any read or write burst in progress must complete. cke must be held high, with ck=low and ?? =high, for the full dur ation of the clock stop mode. one clock cycle and at least one nop or deselect is required after the clock is restarted before a valid command can be issued. notes: 1. prior to ta1, the device is in clock stop mode. to exit, at least one nop is required b efore any valid command. 2. any valid command is supported; device is not in clock suspend mode.
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 80 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved revision history rev page modified description released 0.1 - preliminary release preliminary release 03/ 20 12 0.2 - - a dd idd spec and part number naming 06 / 20 12 0.3 - - idd spec modification. (typical & maximum value) 08/ 20 12 0.4 - - operating temperature ta tc 10/ 20 12 0.5 - - remove pasr 1/8 and 1/16 12/ 20 12 1.0 - - official release 04/ 20 13 1.1 p1 options 1. remove marking column 2. remove vdd/vddq = 1.8v/ 1.8v 3. remove power info 4. 5.4 ns (lpddr370) @ c l= 3 5. 7.5 ns (lpddr266) @ c l=3 6. optional partial array self refresh (pasr) and 7. on - chip temperature sensor to control self refresh rate 06/ 20 13 p5 - 6 ball assignment and package outline drawing 1. b all height of bga60:min =0.25, max=0.4(was: min=0.3, max=0.4) 2. b all height of bga90:min=0.25, max=0.4(was: min=0.3, max=0.4) p7 pin descriptions 1. ba0/ba1: add descripti on ( ba0 and ba1 also determine which mode register is loaded during a load mode register command. ) 2. a10: add des cription ( during a precharge command, a10 determines whether the precharge applies to one bank (a10 low, bank selected by bank address inputs ) or all banks (a10 high) ) 3. vssq: add description ( provide isolated ground to dqs for improved noise immunity. ) p 12 input / output c apacitance 1. follow jesd209b, remove 1.2v i/o description from note1. p13 ac/dc electrical characteristics 1. remove t2 & t4 spec. p14 - 16 idd specifications 1. provide the latest spec from production line test. p25 i - v curve 1. add i - v cur ve for full, three - quarters and half driver strength p27 brief description of initialization sequence 1. new. p31 - p32 partial array self refresh 1. 1/8 array (bank 0 with row address msb=0), and 1/16 array (bank 0 with row address msb=0, and row address ms b - 1=0) . 2. remove 1/8 and 1/16 from mr pasr options p71 - 72 darf directed auto refresh 1.2 p1 4 - 16 idd spec 1. add idd6 spec at 45 o c 2. add idd8 spec at 85 o c 0 9 / 20 13 p17 ac spec 1. tds and tdh_fast/slow:0.48 ns /0.58 ns (was: 0.6 ns /0.7 ns ) all - renew it. 1.3 p1 4 - 15 idd5 1. c orrect the typo of test condition: 140ns (was: 110ns) 10/ 20 13 1.4 p1 - 1. add note 1 12/2013 1.5 p16 idd6 1. add idd6 max spec for pasr full array at 85 o c 12/2013 1.6 p17 tac and tck spec 1. t ac m ax of ddr - 400 cl3: 5.0ns (was: 4.8ns) 2. t ck m in of ddr - 400 cl3: 5.0ns (was: 4.8ns) 06/2014 p1,3,4 - 1. r emove industrial specs and related info
commercial l p ddr 1gb sdram nt6d m 64 m 16 bd / nt6d m 32 m 32 bc 81 version 1. 6 nanya t echnology corporation ? 06 / 20 14 all rights reserved http://www.nanya.com/

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